Overview
IEC 62528:2007 (IEEE 1500-2005) - Standard Testability Method for Embedded Core-based Integrated Circuits - defines a standardized hardware architecture and test protocol for testing embedded IP cores inside a System on Chip (SoC). The standard specifies a scalable wrapper-based approach and leverages the Core Test Language (CTL) to enable communication between core designers and integrators. Published as an IEC/IEEE dual-logo standard, IEC 62528 provides rules and compliance levels for integrating testability into embedded core designs.
Key topics and technical requirements
- Wrapper-based hardware architecture: Defines the core wrapper that isolates cores for test access, including the major wrapper elements:
- WSP (Wrapper Serial Port) and WPP (Wrapper Parallel Port) for test access
- WIR (Wrapper Instruction Register) to select test modes/instructions
- WBY (Wrapper Bypass Register) to speed test data flow
- WBR (Wrapper Boundary Register) to provide boundary scan-like access to core pins
- Instruction set and operation: Specifies WIR instructions and behaviors (examples in the standard include EXTEST, BYPASS, PRELOAD, INTEST, SAFE, CLAMP) and rules for wrapper response to instructions.
- Compliance levels and rules: Introduces two compliance levels and detailed per-terminal, per-core, and per-system compliance definitions for wrapped and unwrapped cores.
- Timing, configuration, and multi-core integration: Includes timing diagrams, WSP/WPP terminal definitions, and guidance for connecting multiple wrapper ports in IEEE 1500 systems.
- Plug-and-Play (PnP) considerations: Describes PnP background, limitations, and how standard instructions interact with PnP features.
- Test data and protocol information: Rules for test pattern information, wrapper protocol metadata, and CTL integration (IEEE P1450.6).
- Informative annexes: Examples of WBR cells, relationship to IEEE 1149.1 (boundary-scan), bubble diagrams, and implementation guidance.
Practical applications
- Enable deterministic, modular testing of embedded IP within SoCs by providing standardized access to core pins and internal test modes.
- Facilitate IP reuse and easier IP integration by defining a common wrapper interface and communication via CTL.
- Reduce integration risk and accelerate bring-up, validation, and manufacturing test of multi-core chips.
- Improve interoperability between core providers, integrators, EDA tool vendors, and test-house workflows.
- SoC architects and design-for-test (DFT) engineers
- IP/core designers and integrators
- Test engineers and manufacturing test teams
- EDA tool developers and test automation vendors
- Semiconductor companies focused on complex multi-core SoCs
Related standards (for further reading)
- IEEE 1500 (original core testability standard) - IEC 62528 is the IEC/IEEE dual-logo adoption
- IEEE 1149.1 (boundary-scan / JTAG) - related boundary-scan concepts and interoperability
- IEEE P1450.6 (Core Test Language, CTL) - protocol for communicating core test information
Keywords: IEC 62528, IEEE 1500, core test language, CTL, SoC testing, embedded core-based integrated circuits, wrapper architecture, WIR, WBR, WSP, WPP, design-for-test (DFT).