IEC 63505:2025 PDF

Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

Название (английский):

IEC 63505:2025

Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

Статус документа:: Действующий
Формат:: Электронный (PDF)
Количество страниц:: 12
Дата публикации:: 8 апреля 2025 г.
Издание:: IEC IS 63505 edition 1 version 1
ICS:: 31.080.30

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Описание (английский):

IEC 63505:2025 gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope. SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI).

Технические детали

Технический комитет: TC 47 - Semiconductor devices
SKU: IEC 63505:2025

Abstract

Overview

IEC 63505:2025 - Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs provides practical, consensus guidance for measuring and conditioning the threshold voltage of N‑channel vertical-structure silicon carbide (SiC) power MOSFETs. The standard addresses measurement methods and pre‑test conditioning that reduce or eliminate VT hysteresis caused by transient traps at the SiC/SiO2 interface. The methods are applicable for positive bias temperature instability (PBTI) testing; negative BTI (NBTI) and VT changes caused by switching events are excluded from the scope.

Key topics and technical requirements

VT hysteresis: SiC MOSFETs can show gate-sweep hysteresis from transient trap effects, complicating true VT-shift evaluation after stress (e.g., BTI).
Conditioning pulse: A positive gate pulse (up to VGS_MAX) applied before measurement minimizes hysteresis; the pulse can make VT effectively “flat” over time.
Test circuits and extraction methods:
- Conventional SMU-based transfer sweep (separate gate and drain): measure IDS while sweeping VGS upward and downward.
- Gate‑drain shorted (GDS) methods: extract VT from the X‑intercept of √IDS vs VGS or by forcing a target IDS for a spot measurement.
Measurement details:
- Small VGS step for sweeps (recommended e.g., 0.1 V) to improve VT accuracy.
- Define a threshold current (Ith) for VT determination.
Recommended timing intervals (from literature and expert consensus):
- For sweep test circuit: t_con = 1–100 ms; t_V

Overview

Key topics and technical requirements

VT hysteresis: SiC MOSFETs can show gate-sweep hysteresis from transient trap effects, complicating true VT-shift evaluation after stress (e.g., BTI).
Conditioning pulse: A positive gate pulse (up to VGS_MAX) applied before measurement minimizes hysteresis; the pulse can make VT effectively “flat” over time.
Test circuits and extraction methods:
- Conventional SMU-based transfer sweep (separate gate and drain): measure IDS while sweeping VGS upward and downward.
- Gate‑drain shorted (GDS) methods: extract VT from the X‑intercept of √IDS vs VGS or by forcing a target IDS for a spot measurement.
Measurement details:
- Small VGS step for sweeps (recommended e.g., 0.1 V) to improve VT accuracy.
- Define a threshold current (Ith) for VT determination.
Recommended timing intervals (from literature and expert consensus):
- For sweep test circuit: t_con = 1–100 ms; t_V

IEC 63505:2025 PDF

Технические детали

Abstract

Overview

Key topics and technical requirements

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Abstract

Overview

Key topics and technical requirements

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