IEC 61523-2:2002 PDF
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
Название (английский):
IEC 61523-2:2002
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
- Статус документа:
- Отменён
- Формат:
- Электронный (PDF)
- Количество страниц:
- 38
- Дата публикации:
- 17 мая 2002 г.
- Издание:
- IEC IS 61523 edition 1 version 1
- ICS:
- 35.240.50
Описание (английский):
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
Технические детали
- Технический комитет
- TC 91 - Electronics assembly technology
- SKU
- IEC 61523-2:2002