Overview
IEC 62530-2:2023 - SystemVerilog Part 2: Universal Verification Methodology (UVM) Language Reference Manual - is an IEC/IEEE dual‑logo standard that defines the Universal Verification Methodology, including the UVM application programming interfaces (APIs) and the UVM Base Class Library (BCL). Built on the IEEE SystemVerilog language (IEEE Std 1800™), this language reference manual standardizes the classes, interfaces and conventions used to create modular, scalable and reusable functional verification environments.
Key topics and technical scope
The standard provides a detailed class and API reference for UVM. Major technical topics include:
- Base classes (uvm_object, uvm_transaction, uvm_component, etc.) for building verification elements
- Reporting and recording mechanisms (report handlers, report servers, transaction databases)
- Factory and object/component creation (UVM factory patterns for run‑time configurability and substitution)
- Phasing and synchronization (predefined phases, domain handling, objections, events and barriers)
- Transaction‑level modeling (TLM) - UVM TLM-1 and TLM-2 interfaces for streaming and layered communication
- Sequencer, sequence and driver abstractions for stimulus generation and control flow
- Policy and utility classes (printers, copiers, packers, comparers, recorders)
- Register layer and register model classes for abstracting memory-mapped registers, maps, fields and memories
- Container classes (queues, pools) and synchronization helpers (heartbeat, callbacks, barriers)
These topics are presented as normative API and class references that verification tools and teams use to implement compliant UVM testbenches.
Practical applications
IEC 62530-2 is used to create consistent, portable, and reusable verification infrastructure across teams and EDA tools. Typical applications:
- Building modular UVM testbenches for ASIC, SoC and FPGA functional verification
- Implementing TLM-based component communication and verification IP (VIP)
- Creating register‑abstraction layers and verification models for memory-mapped IP
- Standardizing reporting, logging and regression infrastructure for large verification projects
- Enabling runtime configurability and component substitution via the UVM factory
Who should use this standard
- Verification engineers and architects designing UVM testbenches
- EDA tool vendors and verification IP developers implementing UVM support
- QA and methodology leads establishing verification process and best practices
- Educators and trainers teaching SystemVerilog/UVM-based verification
Related standards and keywords
- Related: IEEE Std 1800™ (SystemVerilog language standard) - UVM APIs in IEC 62530-2 are based on SystemVerilog
- SEO keywords: UVM, SystemVerilog, Universal Verification Methodology, UVM BCL, functional verification, verification environment, TLM, register model, UVM factory, verification testbench
This IEC/IEEE reference manual is essential for teams seeking a vendor-neutral, standardized specification for building robust UVM verification environments.