Overview
IEC TR 62878-2-8:2021 - "Device embedding assembly technology - Part 2-8: Guidelines - Warpage control of active device embedded substrate" provides practical guidance for understanding and controlling warpage in active device embedded substrates. The report explains warpage origins using the concepts of warpage driving force, warpage resistance and neutral axis, and describes the main parameters (CTE mismatch, layer geometry, die thickness, Cu patterning and process history) that determine warpage behaviour during thermal cycles experienced in package assembly.
Key Topics
- Warpage fundamentals
- Definition of warpage for package-to-board assembly and its impact on solder joint integrity.
- Relationship W ∝ Δα ΔT (warpage proportional to CTE difference and temperature change).
- Driving force vs. resistance
- Driving force: CTE mismatch among die, dielectrics, metal layers and solder.
- Resistance: flexural rigidity (E·I) of the stack - strongly influenced by layer thickness and geometry (warpage ∝ 1/h^3 for beam-like panels).
- Neutral axis
- Role of the neutral axis (z-axis balance of CTE/stiffness) in determining warpage direction and magnitude.
- How shifting the neutral axis changes convex/concave warpage across temperatures.
- Design levers for mitigation
- Material selection and CTE balancing.
- Adjusting die thickness and die-to-panel area ratio.
- Use of patterned or dummy Cu over die locations to balance stiffness and reduce CTE mismatch effects.
- Emphasis on experimental verification and simulation for low-rigidity designs.
- Practical measurement & simulation focus
- Use of measured vs. simulated warpage comparisons for validation of mitigation strategies.
Applications
IEC TR 62878-2-8 is targeted to professionals and teams responsible for device-embedding and package assembly, including:
- Package and substrate designers developing die-embedded substrates for mobile and compact electronics.
- Assembly and process engineers managing reflow, soldering and board mounting where warpage can cause open/short joints.
- Reliability engineers and test labs assessing thermo-mechanical performance and failure risk.
- CAE/simulation analysts modeling thermo-mechanical warpage and validating mitigation measures (dummy Cu, layer stack changes, die thickness).
Use cases include BGA-like packages, embedded die substrates for mobile devices, and any assembly where warpage during heating/cooling influences solder joint formation.
Related Standards
- Normative reference: IEC 60194 (Printed boards design, manufacture and assembly - Vocabulary).
- Part of the IEC 62878 series: see the IEC webstore for other parts in the "Device embedding assembly technology" family.
Keywords: IEC TR 62878-2-8, warpage control, device embedding, active device embedded substrate, warpage driving force, warpage resistance, neutral axis, CTE mismatch, flexural rigidity, dummy Cu, die thickness.