Overview
ISO/IEC TR 15294:2000 is an informative Technical Report that documents methods for data flow control at synchronous and asynchronous DTE–DCE interfaces. It provides guidance to designers and implementers on choosing and implementing local flow-control mechanisms between Data Terminal Equipment (DTE) and Data Circuit-terminating Equipment (DCE). The report focuses on physical‑layer techniques, coordinates material from other standards (notably ITU‑T V.24 and V.43 alignment), and includes tutorial material rather than mandatory prescriptions.
Key topics and requirements
- Scope: guidance for flow control of transmitted and received data, separately for asynchronous and synchronous modes. End‑to‑end flow control and higher‑layer protocols (e.g., HDLC) are out of scope.
- Physical‑layer mechanisms described:
- V.24 interchange circuits (recommended where applicable):
- Circuit 106 - Ready for sending (DCE indicates it cannot accept transmitted data).
- Circuit 133 - Ready for receiving (DTE indicates it cannot accept received data).
- Data‑rate selector circuits (111, 112) to switch between two signalling rates.
- Signal timing circuits (114, 128, 113) used for transmitter/receiver clock control.
- DC3/DC1 character flow control (IRA DC3 = 1/3 to stop, DC1 = 1/1 to resume) - useful in asynchronous streams but unsafe when binary data may be confused with control characters.
- Clock‑rate adjustments and stopping the clock (synchronous mode): halving the clock rate or halting timing to slow or stop the peer transmitter. Notes and cautions cover DTEs with narrow‑band PLLs or alarms on clock stoppage.
- Implementation guidance and cautions:
- Buffer sizing guidance for DCEs when using circuit‑106: suggested remaining buffer capacity ~2,000–4,000 octets, implying total buffers in the range ~4,000–10,000 octets depending on trigger thresholds.
- Emphasis that not all DTEs/DCEs will respond to every mechanism - designers should provide multiple compatible methods where feasible.
- The TR is informative and highlights areas for further study (e.g., binary file transfer ambiguity and duration limits for stopped clocks).
Applications and users
- Practical use cases:
- Designers and firmware engineers of modems, terminal adapters, multiplexers, and serial interface equipment.
- System integrators implementing reliable serial links where DCEs perform compression or error correction.
- Network engineers troubleshooting flow‑control interactions between legacy DTEs and DCEs.
- Benefits:
- Helps prevent buffer overruns/underruns when compression or error correction changes instantaneous throughput.
- Guides interoperable designs for mixed asynchronous and synchronous deployments.
Related standards
- ITU‑T Recommendation V.24 (definitions for interchange circuits).
- ITU‑T V.14 / V.42 (asynchronous-to-synchronous conversion references mentioned).
- ISO/IEC TR 15294 is technically aligned with ITU‑T V.43 but is an informative ISO/IEC Technical Report.
Keywords: ISO/IEC TR 15294, data flow control, DTE‑DCE interface, V.24, DC1 DC3, synchronous flow control, asynchronous flow control, modem buffer sizing, serial interface standards.