Overview
IEC TR 63051:2017 - Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath) - is an IEC Technical Report that defines the main functional requirements for an HDLMath language and compares existing HDLMath implementations from a designer’s perspective. Its purpose is to accelerate the standardization of a mathematical-algorithm hardware description language (HDLMath) and to help establish a robust system level modeling and verification environment for electronic systems.
Key topics and technical requirements
The report organizes requirements and comparisons around practical language and verification needs, including:
- Definition and positioning of HDLMath as a system-level language for describing and verifying behavior using mathematical algorithms.
- Functional requirements such as:
- expressive mathematical expressions and functions (complex numbers, matrices, transforms),
- support for various precision types and precision-aware computation,
- exception and error handling and overflow strategies,
- native support for multi-dimensional arrays and advanced mathematical functions,
- mixed numerical and symbolic computations,
- modeling of feedback processes,
- integration of user‑defined functions in C-code,
- a structured verification/test-bench environment for system-level validation.
- Comparison of current HDLMath languages (identified generically in the report as HDLMath1/2/3) and examples of existing environments such as MATLAB/Simulink, FinSimMath and SystemC-AMS.
- Guidance to include HDLMath in the Bird’s-eye View of Design Languages (BVDL) landscape for SoC design flows.
Applications and practical value
IEC TR 63051:2017 is focused on use cases where mathematical modeling improves design productivity and accuracy:
- System-on-Chip (SoC) behavioral modeling and algorithm verification
- Algorithm designers for ASIC and FPGA implementations
- Signal processing, control systems, and analog/mixed‑signal modeling
- Early-stage system architecture exploration and performance validation
- Bridging algorithmic models to register-transfer level (RTL) languages and implementation flows
The standard helps teams reduce design iterations, supports reproducible verification workflows, and enables clearer mapping from mathematical specifications to hardware implementation.
Who should use this standard
- System architects and algorithm developers
- Verification engineers and test-bench authors
- EDA tool vendors and language designers
- Standards committees and organizations defining SoC design flows
Related standards
- IEC 61691-1-1 (VHDL)
- IEC 62530 (SystemVerilog)
- IEC TR 62856 (BVDL - Bird’s-eye View of Design Languages)
- SystemC and SystemC-AMS ecosystems
Keywords: IEC TR 63051:2017, HDLMath, hardware description language, mathematical algorithm, system level modeling, verification, SoC, ASIC, FPGA, design automation.